1. Field of the Invention
This invention relates to a current sensor circuit and, more particularly, to a Built In Current Sensor Circuit for use in quiescent power supply current, or IDDQ, testing of integrated circuits.
2. Description of the Background Art
Presently, there are several different types of testing methods for detecting defaults in integrated circuits. However, one particular method has been widely accepted and successful in the electronics industry. This one particular method comprises a complementary metal oxide semiconductor (CMOS) integrated circuit test method which is known as quiescent power supply current, or IDDQ, testing. IDDQ testing achieves high fault coverage and is used to detect physical defects in integrated circuits which are not detectable using logic or functional test methods. Although IDDQ testing has been used effectively on CMOS integrated circuits (ICs) with submicron feature sizes (integrated circuits utilizing dimensions less than 1 .mu.m), its effectiveness on ICs scaled to the deep submicron regime (typically L.sub.effective &lt;0.5 .mu.m) has not been studied extensively.
As CMOS devices are scaled to the deep submicron regime, IC reliability can be reduced due to second order effects such as hot carriers and impact ionization. Although IDDQ testing is a potential test method for detecting leakage current in scaled ICs, the area overhead, the circuit performance, and the fault detectability penalties are particularly important in scaled ICs. These listed areas are the metrics which are used to evaluate the effectiveness of IDDQ testing along with fault diagnosability.
Testing very large scale integration (VLSI) and ultra large scale integration (ULSI) integrated circuits (ICs) is becoming increasingly more difficult, more time consuming, and more costly. This is due to increased circuit complexity and circuit densities, and reduced circuit feature sizes. Future VLSI/ULSI ICs will be tested using either existing, refined, or newly developed and more cost effective test methods and equipment. In addition, a greater emphasis must be placed on implementing design-for-test (DFT) strategies early in the design cycle due to the heavy burden and costs associated with back-of-the-line testing.
There are presently four types of tests performed on CMOS ICs for detecting and locating defects and faults. They are functional, logic, parametric, and IDDQ tests. The tests are performed in combinations at wafer-, bare-, die-, packaged-, assembly-, and system-levels. Functional IC tests are designed to verify whether the IC performs its intended function. Logic tests verify the logic operation of gates and registers, while AC and DC parametric tests are used to measure time-, voltage-, and current-varying parameters associated with the operational limits of the IC. Test parameters include propagation delay, operating current, and rise and fall time. Although IDDQ is actually a parametric test, it is considered unique due to its sensitivity to a specific class of physical defects to which CMOS ICs are susceptible.
IDDQ testing is performed by applying a predetermined set of test patterns to the primary inputs of a CMOS IC. The patterns, or vectors, are designed to force adjacent uncoupled nodes to opposite logic states. This creates a current leakage path from VDD to GND if the adjacent nodes become coupled through a short or bridge. A fault is detected by measuring the increased quiescent steady state current level at the VDD or VSS pins. The technique is effective since a broad class of physical defects is known to manifest itself as increased quiescent current levels easily observable using a sensitive current monitor. The technique also provides a high level of observability since it is unnecessary to propagate internal faults to output pins of the IC for observation. In addition, the number of test patterns required to provide high fault coverage in IDDQ testing is significantly fewer than those required for full functional and logic testing.
Although IDDQ testing is used successfully on CMOS ICs with feature sizes of 1 .mu.m and greater, very little effort has been invested in applying IDDQ test monitoring to deep submicron (below 0.5 .mu.m) CMOS ICs. This is significant since physical defects and parametric variations such as hot electrons, gate induced drain leakage (GIDL), and excessive subthreshold leakage result in increased quiescent current. This poses a reliability concern since CMOS ICs with minimum feature sizes down to 0.1 .mu.m are expected commercially in the near future. Thus, it is important to effectively develop and apply IDDQ measurements as a test and diagnostic tool for deep submicron CMOS ICs.
Deep submicron CMOS technology is becoming the dominant technology for ULSI integrated circuits to be used in future applications. It promises faster circuit operation, lower power consumption, and more processing capability per chip than present CMOS technology. The development of deep submicron CMOS ICs requires a very close relationship between design, process, and test engineering. In addition, an in-depth understanding of MOS device physics and modeling for deep submicron process technology is imperative. This is especially true since some types of defects are difficult to detect using conventional commercial tools. These are low current defects which can cause catastrophic system failure if undetected. Thus, reliability concerns increase dramatically as circuit and feature sizes are scaled to the deep submicron regime.
Some reliability concerns in deep submicron ICs are caused by short channel effects which are far more damaging in scaled devices than in near-micron devices. A primary reliability concern in scaled devices is hot electrons. These are electrons in the channel region which are accelerated towards the gate oxide under the high field strength, penetrate the gate oxide, and ultimately become trapped therein. These trapped charges have the negative effect of raising the threshold voltage and reducing the drain current and device transconductance. Despite the success of applying conventional scaling rules to devices scaled from 2 .mu.m to 1 .mu.m, the same rules do not apply when devices are further scaled down to deep submicron features.
Thus, IDDQ testing has become a proven and cost effective CMOS IC screening tool. Although IDDQ testing is used successfully with near-micron CMOS processes, its feasibility in deep submicron (L.sub.effective &lt;0.5 .mu.m) CMOS processes has not been fully developed. In expanding the utilization of IDDQ testing into the deep submicron regime, many problems exist with the current techniques and circuit designs presently being used in the industry.
IDDQ testing imposes several penalties on present day CMOS ICs including circuit under test (CUT) performance degradation, increased IC area overhead, and low test speed versus current resolution sensing ratio. Notwithstanding, the advantages of IDDQ testing have been shown to overshadow the penalties in near micron processes.
However, as IC feature sizes are scaled down to deep submicron levels, the penalties associated with IDDQ testing increase significantly. This is due to higher operating speeds, greater gate density, and lower operating voltages than in near micron ICs. In addition, the class of current leakage faults in deep submicron process technology is extended to further include certain second order and short channel effects such as hot carriers and impact ionization. These additional faults are due to strong device interdependencies and specification tolerances resulting from scaled features. Thus, the problems associated with the IDDQ testing techniques and circuit designs currently being used in the industry in contemporary CMOS technologies severely limit the use of IDDQ testing in deep submicron applications.
There are several approaches to the application of IDDQ testing of ICs. One approach is to monitor the steady state current externally with an off-the-shelf high resolution current monitor. Another approach is to monitor the steady state current internally by way of designing a current monitor into the fundamental circuit or by placing the current monitor circuit on a separate chip adjacent the circuit under test as is performed in multichip module designs.
The external testing approach presents several problems which renders its use in deep submicron applications impractical. External monitoring of the IDDQ current requires special testing hardware and significantly longer test times per cycle due to waiting for the circuit under test to settle into its steady state before taking the measurement. Thus, for deep submicron applications, it is the internally located current monitor approach that presents the most efficient means for overcoming the current problems associated with deep submicron IDDQ testing. The class of internal IDDQ monitors are built as dedicated embedded built in current sensor (BICS) circuits designed around a set of IC-specific specifications. Implementing efficient and cost effective BICS circuits requires a sound and well organized approach. The BICS should handle two extreme situations. During functional testing, the circuit under test draws a large transient current. The BICS must be capable of handling this large current without introducing a significant voltage drop across the sensing element. Once the current settles into a steady-state, the BICS circuit must be capable of detecting the small leakage currents caused by a fault. To meet these two requirements, the BICS circuit should have a small resistance whenever a large transient current occurs and a large equivalent input resistance when detecting faulty leakage current. It is therefore impractical to employ a linear element such as a resistor to both sink and detect the current since both conditions cannot be met simultaneously.
Generally, these internal current monitors are fundamentally custom analog BICS circuits designed with standard passive and active components such as capacitors, resistors, and operational amplifiers. In short, advantages of internal current monitors include their ability to operate at higher test, operate under wider current ranges, exhibit small footprints, and operate under very low power consumption. These are important design attributes since the current monitors may reside on the same piece of silicon, or substrate, as the circuit under test. In the case of a partitioned circuit requiring multiple current sensors, specific design tradeoffs can be made to optimize the circuit area and the number of gates per monitor.
Representative examples of internal built in current sensor circuits are disclosed in U.S. Pat. No. 5,025,344, issued to Maly and Nigh, U.S. Pat. No. 5,371,457, issued to Lipp, and U.S. Pat. No. 5,392,293, issued to Hsue, the disclosures of which are hereby incorporated by reference herein. Further, other representative examples of internal built in current sensor circuits are disclosed in the technical journal articles of: Brown, B. D., and McLeod, R. D., "Built-in Current Mode Circuits for Iddq Monitoring", Cust. Integ. Ckts. Conf. pp 30.6.1-6.4, 1993; Hao, H., and McCluskey, E. J., "Anaylsis of Gate Oxide Shorts in CMOS Circuits", IEEE Tran. on Computers, vol 42, no. 12, pp. 1510-1516, December 1993; Hsue, C., and Lin, C., "Built-In Current Sensor for Iddq Test in CMOS", IEEE Intl.Test Conf, pp. 635-641, 1993; Maly, W., and Patyra, M., "Design of ICs Applying Built-In Current Testing", Jnl. of Elec. Test, Thry. & Applic., pp. 111-120 December 1992; Mao, W., and Gulati, R. K., "QUIETEST: A Methodology for Selecting Iddq Test Vectors", Jnl. Elec. Test Thry. and Applic., pp. 63-71, December 1992; Menon, S. M., et. al., "The Effect of Built-In Current Sensors (BICS) on Operational and Test Performance", IEEE Conference on VLSI Design, pp. 187-190, January 1994; Miura, Y., and Kinoshita, K., "Circuit Design for Built-in Current Testing", Proc. IEEE Intl. Test Conf, pp. 873 881, 1992; Nigh, P., and Maly, W., "Test Generation for Current Testing", IEEE Design & Test of Computers, pp 26-38, February 1990; Rius, J., and Figueras, J., "Proportional BIC Sensor for Current Testing", Jnl. Elec. Test Thry. & Applic., pp. 101-110, December 1992; Shen, T. L., Daly, J. C., and Lo, J. C., "A2-ns Detecting Time, 2-.mu.m CMOS Built-In Current Sensing Circuit", IEEE Jnl. Sld. St. Ckts., Vol. 28, No. 1, pp. 72-77, January 1993; and Tang, J., Lee, K., and Liu, B., "A Practical Current Sensing Technique for IDDQ Testing", IEEE Trans. on VLSI Systems, Vol. 3, No. 2, pp. 302-310, June 1995, the disclosures of which are hereby incorporated by reference herein.
While all of the above referenced examples of internal built in current sensor circuits have been used in near-micron ICs, none of them are suitable for use in deep submicron applications due to their lack of current sensitivity, excessive area overhead, required additional amplifiers and summing circuits, excessive circuit complexity and larger operating power requirements. Additionally, besides having the above listed inadequacies, the built in current sensor circuit disclosed by Shen further includes a diode in the detecting portion of the sensor circuit which can prevent reliable circuit operation in ICs operating at 1 to 2 volts due to the minimum 0.65 volts across the diode. This minimum voltage limits the sensitivity and ultimate current range of the detecting portion of the circuit. ICs having feature sizes in the deep submicron region generally operate at low supply voltage levels.
Therefore, it is an object of this invention to provide an improvement which overcomes the aforementioned inadequacies of the prior art devices and provides an improvement which is a significant contribution to the advancement of IDDQ fault testing art.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that is less complex and inexpensive to manufacture.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that has high reliability.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that provides for highly accurate IDDQ testing.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that has a small footprint and reduces the area overhead required in the IC thereby facilitating the configuring of smaller partition sizes resulting in larger numbers of partitions and higher test resolution for improved defect diagnosis.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that provides for fast IDDQ test speeds suitable for large scale deep submicron integrated circuit testing whereby simultaneous testing of multiple partitions is possible using standard test patterns. Ultimately, real time IDDQ fault detection and diagnosis is provided for.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that requires less test patterns to be applied to the IC for complete IDDQ testing.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that provides for delay fault testing.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that provides a high measurement sensitivity for IDDQ currents and is readily used in conjunction with existing external current monitors.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that has a wide current range capable of being sensed so to facilitate the measuring of large scale integrated circuits having a large amount of gates.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that is capable of handling the transient currents of the circuit under test.
Another object of this invention is to provide a built in current sensor circuit and method for use in testing integrated circuits for defects that is readily adaptable to multichip module (MCM) technology.
Another object of this invention is to provide a built in current sensor circuit for use in testing integrated circuits for defects by sensing current increases caused by the defects, the built in current sensor circuit comprising in combination: detecting means for detecting current flow through the integrated circuit and providing a representative signal therefor; reference source means for providing a reference threshold signal, the reference source means being electrically coupled relative to the detecting means; comparator means for comparing the reference threshold signal to the representative signal, the comparator means being electrically coupled to the detecting means and electrically coupled to the reference source means; and an active output load electrically coupled to the comparator means, the active output load being sized to draw a disproportionately larger current when turned on than the current caused by the defect in the integrated circuit, whereby the comparator means turns on the active output load when the representative signal is determined to be larger than the reference threshold signal and the current draw of the active output load is resultantly sensed indicating that the integrated circuit is defective.
The foregoing has outlined some of the pertinent objects of the invention. These objects should be construed to be merely illustrative of some of the more prominent features and applications of the intended invention. Many other beneficial results can be obtained by applying the disclosed invention in a different manner or by modifying the invention within the scope of the disclosure. Accordingly, other objects and a more comprehensive understanding of the invention may be obtained by referring to the summary of the invention, and the detailed description of the preferred embodiment in addition to the scope of the invention defined by the claims taken in conjunction with the accompanying drawings.